Phase change memory programming circuit with improved speed

doi:10.1007/s44275-024-00023-y

Moore and More ›› 2025, Vol. 1 ›› Issue (3): 208-218.DOI: 10.1007/s44275-024-00023-y

• Original Article • Previous Articles Next Articles

Phase change memory programming circuit with improved speed

Xinyu Yang^1,2, Yu Lei¹, Qiuyao Yu^1,2, Qian Wang¹, Houpeng Chen¹, Zhitang Song¹

1. State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China;
2. Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, China

Received:2024-09-24 Revised:2024-12-12 Accepted:2024-12-22 Online:2025-11-29 Published:2025-01-15
Contact: Yu Lei,E-mail:leiyu@mail.sim.ac.cn
Supported by:
This work was supported by the National Key R&D Program of China under Grants 2023YFB4404500, 2023YFB4502903, 2023YFB4502202, and 2022ZD0117602; the National Natural Science Foundation of China under Grants 92164302, 62274170, 62204251, and 62174168; the Youth Innovation Promotion Association CAS under Grant 2022233; the Strategic Priority Research Program of the Chinese Academy of Sciences under Grants XDB44010200 and XDB06700300; the Science and Technology Council of Shanghai under Grants 23XD1404700, 23JC1400900, and 22DZ2229009; the Shanghai Rising-Star Program under Grant 24QA2711200; and the Autonomous Deployment Project of the State Key Laboratory of Materials for Integrated Circuits under Grant NKLJC-Z2023-B04.

Phase change memory programming circuit with improved speed

Xinyu Yang^1,2, Yu Lei¹, Qiuyao Yu^1,2, Qian Wang¹, Houpeng Chen¹, Zhitang Song¹

1. State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China;
2. Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, China

通讯作者: Yu Lei,E-mail:leiyu@mail.sim.ac.cn
作者简介:Xinyu Yang received his B.S. degree in electronic science and technology from Nanjing University 358 of Posts and Telecommunications, Nanjing, China, in 2023. He is currently pursuing a master’s 359 degree in electronic information with the University of Chinese Academy of Sciences, Beijing, 360 China. His research interests include the analysis of programming circuits for PCM.
Yu Lei received his B.S. degree in electronics from the University of Science and Technology of China (USTC), Hefei, China, in 2012, and an M.S. degree in IC engineering and Ph.D. degree in microelectronics from Shanghai Institute of Micro-system and Information Technology (SIMIT), Chinese Academy of Sciences (CAS), Shanghai, China, in 2015 and 2018, respectively. He joined the State Key Laboratory of Materials for Integrated Circuits, SIMIT, CAS, Shanghai, China, in 2018, where he is currently an associate professor. He has authored over 30 research papers and holds 40 patents. His current research interest includes circuit designs for volatile and nonvolatile memory, phase change memory, 3-D integration, memristor-based circuits, and device models for artificial intelligence. He is a member of the IEEE Solid-State Circuits Society and the IEEE Circuits and Systems Society. He was a recipient of the Outstanding Science and Technology Achievement Prize of the CAS in 2022, the Youth Innovation Promotion Association of CAS in 2022, the Star of SIMIT in 2022, the First Prize in the Science and Technology Prize of the Chinese Materials Research Society in 2019, the Shanghai Youth Science and Technology Talent (Sailing Program) in 2019, the Outstanding Graduate of Shanghai in 2018, and the UCAS-BHPB Scholarship in 2017. He has served as a reviewer for IEEE Journal of Solid State Circuits, IEEE Open Journal of the Solid-State Circuits Society, IEEE Transactions on Circuits and Systems I–Regular Papers, IEEE Transactions on Circuits and Systems II–Express Briefs, IEEE Transactions on Very Large Scale Integration Systems, IEEE Symposium on Circuits and Systems, IEEE Transactions on Device and Materials Reliability, and Nature Energy.
Qiuyao Yu received her B.S. degree in electronic science and technology from Hunan University, Changsha, China, in 2020. She is currently pursuing a Ph.D. degree in microelectronics and solid state electronics with the University of Chinese Academy of Sciences, Beijing, China. Her current research interests include sensing margin analysis and sensing circuits for 3D PCM.
Qian Wang received her Ph.D. degree from Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China, in 2016. She is currently with SIMIT, CAS, Shanghai.
Houpeng Chen received his Ph.D. degree from Shanghai Jiao Tong University, Shanghai, China, in 1996. He joined Shanghai Belling Co., Ltd., Shanghai, in 2002. He is currently with SIMIT, CAS, Shanghai. In December 2008, he joined the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences. His research interests include analog integrated circuit design and memory integrated circuit design.
Zhitang Song received his Ph.D. degree from the Electronic Materials Research Laboratory, Xi’an Jiaotong University, Xi’an, China, in 1997. He is currently with the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China as the Director of the State Key Laboratory of Functional Materials for Informatics. He has taken a lead in conducting research and development of PCRAM, and cultivated and organized the 100-person high-level research and development team, integrating industry, university, and research.
基金资助:
This work was supported by the National Key R&D Program of China under Grants 2023YFB4404500, 2023YFB4502903, 2023YFB4502202, and 2022ZD0117602; the National Natural Science Foundation of China under Grants 92164302, 62274170, 62204251, and 62174168; the Youth Innovation Promotion Association CAS under Grant 2022233; the Strategic Priority Research Program of the Chinese Academy of Sciences under Grants XDB44010200 and XDB06700300; the Science and Technology Council of Shanghai under Grants 23XD1404700, 23JC1400900, and 22DZ2229009; the Shanghai Rising-Star Program under Grant 24QA2711200; and the Autonomous Deployment Project of the State Key Laboratory of Materials for Integrated Circuits under Grant NKLJC-Z2023-B04.

Abstract

Abstract: Phase change memory (PCM) is considered one of the most promising next-generation non-volatile memory types for storage-class memory due to its many advantages, including ultrafast programming, long data retention, high storage density, low power consumption, and compatibility with standard CMOS processes. However, in conventional PCM programming circuits, the first programming operation after power-on suffers from a slow rise time in the programming pulse due to the lack of bias voltage pre-charging in the current source circuit, which leads to reduced consistency in the programming of phase change cells. In this study, we developed two solutions to address the issue associated with conventional PCM programming circuits. We also analyzed conventional programming circuit schemes and designed a PCM programming circuit with improved speed using the SMIC 40 nm CMOS process. The results demonstrated that compared with conventional programming circuits, the PCM programming circuit with improved speed reduced the rise time of SET pulses from 29.6 ns to 7.3 ns and the rise time of RESET pulses from 13.6 ns to 3.1 ns. In addition, it improved the consistency of the programming phase change cells and reduced the power consumption from 11.93 mW to 10.35 mW.

Key words: Programming circuit, Improved speed, Rise time, Circuit design, Phase change memory

摘要： Phase change memory (PCM) is considered one of the most promising next-generation non-volatile memory types for storage-class memory due to its many advantages, including ultrafast programming, long data retention, high storage density, low power consumption, and compatibility with standard CMOS processes. However, in conventional PCM programming circuits, the first programming operation after power-on suffers from a slow rise time in the programming pulse due to the lack of bias voltage pre-charging in the current source circuit, which leads to reduced consistency in the programming of phase change cells. In this study, we developed two solutions to address the issue associated with conventional PCM programming circuits. We also analyzed conventional programming circuit schemes and designed a PCM programming circuit with improved speed using the SMIC 40 nm CMOS process. The results demonstrated that compared with conventional programming circuits, the PCM programming circuit with improved speed reduced the rise time of SET pulses from 29.6 ns to 7.3 ns and the rise time of RESET pulses from 13.6 ns to 3.1 ns. In addition, it improved the consistency of the programming phase change cells and reduced the power consumption from 11.93 mW to 10.35 mW.

关键词: Programming circuit, Improved speed, Rise time, Circuit design, Phase change memory

Xinyu Yang, Yu Lei, Qiuyao Yu, Qian Wang, Houpeng Chen, Zhitang Song. Phase change memory programming circuit with improved speed[J]. Moore and More, 2025, 1(3): 208-218.

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Phase change memory programming circuit with improved speed

Phase change memory programming circuit with improved speed

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