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    GaN-on-diamond technology for next-generation power devices
    Kangkai Fan, Jiachang Guo, Zihao Huang, Yu Xu, Zengli Huang, Wei Xu, Qi Wang, Qiubao Lin, Xiaohua Li, Hezhou Liu, Xinke Liu
    Moore and More    2025, 1 (4): 370-394.   DOI: 10.1007/s44275-024-00022-z
    Abstract32)      PDF(pc) (3949KB)(5)       Save
    Gallium nitride (GaN)-based power devices have attracted significant attention due to their superior performance in high-frequency and high-power applications. However, the high-power density in these devices often induces severe self-heating effects (SHEs), which degrade their performance and reliability. Traditional thermal management solutions have struggled to efficiently dissipate heat, thereby leading to suboptimal real-world performance compared with theoretical predictions. To address this challenge, diamond has emerged as a highly promising substrate material for GaN devices, primarily due to its exceptional thermal conductivity and mechanical stability. GaN-on-diamond technology has a thermal conductivity of 2 200 W/m/K and it significantly enhances heat dissipation at the chip level. In this review, we provide a systematic overview of the two main integration methods for GaN and diamond: bonding and epitaxial growth techniques. Moreover, we elaborate on the impact of thermal boundary resistance (TBR) at the interface. According to the diffuse mismatch model, the TBR of GaN-on-diamond interfaces can be as low as 3 m2K/GW, which is markedly superior to silicon carbide substrates. In addition, novel techniques such as patterned growth, nanocrystalline diamond (NCD) capping films, and diamond passivation layers have been explored to further enhance thermal management capabilities. We also consider the roles of intermediate dielectric layers in reducing TBR, promoting diamond nucleation, and protecting the GaN layer. Thus, in this review, we summarize the current state of research into GaN-on-diamond technology, highlighting its revolutionary impact on thermal management for power devices and providing new pathways for the development of high-power GaN devices in the future.
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    Stability of p-GaN gate AlGaN/GaN HEMTs under static and dynamic drain stress
    Linfei Gao, Xiaohua Li, Wei He, Xinbo Xiong, Huaibao Yan, Hsien-Chin Chiu, Zhanwu Yang, Lixuan Chen, Qiubao Lin, Kaifeng Wang, Hezhou Liu, Xinke Liu
    Moore and More    2025, 1 (3): 290-299.   DOI: 10.1007/s44275-025-00029-0
    Abstract18)      PDF(pc) (1746KB)(0)       Save
    In this article, we report the investigation into the stability of p-GaN gate high electron mobility transistors (HEMTs) with an internal integrated gate circuit that led to the design of a capacitance-based circuit to address threshold voltage shifts (ΔVTH). Pulse I-V measurement revealed a notable positive gate VTH shift of 0.7 V as the drain voltage increased from 0 to 650 V, highlighting the impact of drain bias on VTH instability. Through the investigation of drain bias-induced VTH instability and the behavior of carriers being transported within the gate region, it was found that the maximum ΔVTH is 0.4 V when a 200-V drain bias is applied; after stress removal, ΔVTH diminishes gradually due to the discharge of capacitance, and holes enter the p-GaN layer to mitigate the depletion of holes. The integration of passive components and p-GaN gate HEMT circuits is suggested to address VTH instability in enhancement-mode HEMT devices. The reliability of power devices is essential for their acceptance in emerging applications.
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