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2026 , Vol. 2 >Issue 1: 1 - 14

DOI: https://doi.org/10.1007/s44275-025-00028-1

ORIGINAL ARTICLE

A reconfigurable heterogeneous in-memory computing architecture for variable precision computation: a software-hardware co-design approach

  • Yizhe Chen ,
  • Hanjie Liu ,
  • Saiya Wang ,
  • Jinyao Mi ,
  • Xiaodi Xing ,
  • Yuexi Lv ,
  • Aifei Zhang ,
  • Lichuan Luo ,
  • Yong Pei ,
  • Minghua Tang ,
  • Wang Kang
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  • 1 School of Integrated Circuit Science and Engineering, Beihang University , Beijing 100191, China
    2 The College of Chemistry, Xiangtan University , Xiangtan 411105, Hunan, China
    3 Zhicun Research Lab , Hangzhou 311101, China
    4 State Key Laboratory of Wireless Mobile Communications (CICT) , Beijing 100191, China
    5 School of Materials Science and Engineering, Xiangtan University , Xiangtan 411105, Hunan, China
Yizhe Chen received a B.S. degree from the College of Electrical and Information Engineering in Zhengzhou University of Light Industry, in 2021. He is currently working toward an M.S. degree in the College of Chemistry at Xiangtan University. His research interests include noise modeling and optimization algorithms in analog in-memory computing, quantization, and training of neural networks.
Hanjie Liu received a B.S. degree in measurement and control technology and instrumentation from Wuhan Textile University, in 2016. He is currently working toward an M.S. degree in information and electronics at Beihang University. His research interests include AI compiler design, simulator design, and system co-design of computing in memory.
Saiya Wang received a B.S. degree in communication engineering from Hunan University in 2024. Currently, she is working toward an M.S. degree in science and engineering of integrated circuits at Beihang University. Her research mainly focuses on inmemory-computing circuit design and efficient deep learning.
Jinyao Mi received a B.S. degree in integrated circuit design and integrated system from Beihang University, Beijing, in 2024. Currently, he is working toward a Eng.D. degree in integrated circuit engineering at Beihang University. His research mainly focuses on analog in-memory-computing circuit.
Xiaodi Xing received a Ph.D. degree in communications and information systems in 2014, and a bachelor’s degree in electronic engineering in 2006, both from Beihang University, Beijing. He joined Zhicun Research Lab in 2018 after 5 years’ experience in IBM China system center, and has been working on the architecture design of neural network processor units built on computing-in-memory (MPU) ever since. His current interests include visual processing network and LLM model chip design and architectural optimization.
Yuexi Lv received a B.S. degree from the School of Electronic Science and Engineering in Nanjing University in 2015, and an M.S. degree from the State Key Laboratory of Superlattices and Microstructures in the Institute of Semiconductors, in 2018. His research interests include noise modeling and optimization algorithms in analog inmemory computing, quantization and training of neural networks.
Aifei Zhang received an M.S. degree from the School of Information and Electronics in the Beijing Institute of Technology, Beijing, in 2017. He is currently working in the Zhicun Research Lab, Beijing. His research interests mainly include AI compilers, frameworks, high-efficiency computing and heterogeneous cooperative computing platforms.
Lichuan Luo received a B.S. degree in integrated circuit design and integrated systems from Xidian University, Xi’an, Shaanxi, in 2013, and an M.S. degree in microelectronics and solid-state electronics from the Institute of Semiconductor, Chinese Academy of Sciences, Beijing, in 2016. He received his Ph.D. degree from Beihang University, Beijing, in 2024. He is an ASIC Design Engineer with China Information and Communication Technology Group Co., Ltd. His research interests include computingin-memory, RISC-V, embedded deep learning, and reconfigurable computing.
Yong Pei received a B.S. degree from the College of Chemistry in Xiangtan University, in 2001, and a Ph.D. degree from the Institute of Theoretical and Computational Chemistry in Nanjing University, in 2006. His research interests include theoretical computational simulation of the structural evolution of clusters, electronic structure, photophysical and chemical properties, and metal exchange mechanisms.
Minghua Tang received a B.S. degree in physics and a Ph.D. degree in materials physics and chemistry from Xiangtan University, Hunan, China, in 1988 and 2007, respectively. He is currently with the School of Materials Science and Engineering, Xiangtan University, Xiangtan, Hunan, and was a Visiting Professor at the Institute of Microelectronics of Tsinghua University, China (2003-2004), Tokyo Institute of Technology, Japan (2008- 2009) and Nanyang Technological University, Singapore (2011), with research work focused on the fabrication and the characteristics of ferroelectric thin film memory with 65 nm process. His research interests include ferroelectric thin film memory, resistive random access memory, and neuromorphological devices for computing-in memory application and power devices.
Wang Kang (Senior Member, IEEE) received a double Ph.D. degree in physics from the University of Paris- Sud, France, and in microelectronics from the Beihang University, Beijing. He is an Associate Professor with the School of Integrated Circuit Science and Engineering, Beihang University. His research interests include spintronics and its related devices, circuits, and architectures. He has coauthored three book chapters, over 40 Chinese patents, and over 100 scientific papers.
*Wang Kang (wang.kang@buaa.edu.cn)

Received date: 2024-10-14

  Revised date: 2025-01-03

  Accepted date: 2025-01-13

  Online published: 2025-07-14

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Abstract

In-memory computing (IMC) has emerged as a promising approach for accelerating deep neural network (DNN) inference by relocating computations to memory arrays. However, the efficacy of analog IMC diminishes when higher computational precision is required due to inherent device non-idealities. In this paper, we present a reconfigurable heterogeneous architecture that integrates a digital computing unit (DCU) with an analog IMC unit (AIMCU). The computational data is partitioned into most significant bits (MSBs) and least significant bits (LSBs); the sparse MSBs are processed by the DCU with lossless precision, and the dense LSBs are computed by the AIMCU for high energy efficiency, thereby enhancing inference accuracy and optimizing area efficiency. The architecture also features multiple modes that support variable-precision input splitting and weight splitting computation. Additionally, by leveraging hardware characteristics, we have developed several optimization strategies for neural network deployment, including parameter splitting, shifting algorithms, and sparse weight mapping. The experimental results show that the perceptual evaluation of speech quality (PESQ) of the deep complex convolution recurrent network (DCCRN) improved by 28.98%, while the peak signal-to-noise ratio (PSNR) of the super-resolution network (SRN) increased by 17.27%. Compared to previous state-of-the-art (SOTA) work, the reconfigurable heterogeneous-IMC-based system on a chip (SoC) demonstrates a significant improvement in energy efficiency while achieving accuracy close to that of pure digital computing.

Key words： In-memory computing; DNN; Heterogeneous; Accuracy improvement; Parameter split

Cite this article

Yizhe Chen , Hanjie Liu , Saiya Wang , Jinyao Mi , Xiaodi Xing , Yuexi Lv , Aifei Zhang , Lichuan Luo , Yong Pei , Minghua Tang , Wang Kang . A reconfigurable heterogeneous in-memory computing architecture for variable precision computation: a software-hardware co-design approach[J]. Moore and More, 2026 , 2(1) : 1 -14 . DOI: 10.1007/s44275-025-00028-1

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